11.2 Physical Memory Map

The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed and are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 11-1. Physical Memory Map
MemoryStart addressSize in KB
PIC32CZ8xyyPIC32CZ4xyyPIC32CZ2xyy
Embedded Flash0x08000000819240962048
Embedded SRAM0x2000000010241024512
Peripheral Bridge A0x44000000819281928192
Peripheral Bridge B0x44800000819281928192
Peripheral Bridge C0x45000000819281928192
Peripheral Bridge D0x45800000819281928192
Peripheral Bridge E0x46000000819281928192
Peripheral Bridge F0x46800000819281928192
Independent Peripherals0x4F000000163841638416384