11.3 SRAM Memory Configuration
Retention
Depending on the application and power budget needs, system memory can be retained in Standby mode or Hibernate mode. The amount of the SRAM retained in this mode is software selectable, by writing the RAMCFG bits in the Power Manager Standby Configuration register and Hibernate Configuration register.
RAM Error Correction
For safety applications, the PIC32CZ CA family embeds error correction codes (ECC) to detect and correct single bit errors, or to enable dual error detection for the system memory. The ECC is software selectable through the RAM ECCDIS bit in the NVM User Configuration. For additional information, refer to “NVM User Page Mapping - Dedicated Entries”.