13.4 Peripheral Dependencies
| Peripheral Name | Base Address | NVIC IRQ Index: Source | MCLK AXI/APB Clocks Index: MCLK.CLKMSK0[20] | PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | Power Domain |
|---|---|---|---|---|---|
| MCRAMC - Multi-Channel RAM Controller | 0x4482 2000 (APB B) | 37 : INT | MCLK.CLKMSK0[20] | 17 | VDDREG |
- Register Field: MCLK.CLKMSK{index/32}.MASK[index mod 32].
Power Management
The memory controller does not provide any power management features. If the memory controller clock is running during sleep then the memory controller is active.
Clocks
The MCRAMC operates synchronous to the system and uses the BMX clock (CLK_BMX). The MCRAMC does not generate clock requests.
Debug Operation
The debugger is allowed read and write access to the MCRAMC control registers regardless of the PAC write-access settings.
Register Access Protection
All registers with write-access can be write-protected optionally by the PAC. Optional write-protection by the PAC is denoted by the “PAC Write-Protection” property in each individual register description. PAC write-protection does not apply to accesses through an external debugger.