16.9 Programming

For each bus system, programming the Flash or RAM memories is only possible when the debugger access level is sufficient to access the desired resource. If MEM-APx is selected by the DP and if DAL.CPUx is equal to:

  • 0x2: debugger can access all areas in the CPU bus system.
  • 0x0: If the debugger targets the MEM-AP0 then it can only access the DSU external address space making it possible to communicate with the Boot ROM after reset. If debugger targets the MEM-AP1 then all transactions results in a DAP fault.

A typical programming procedure, when DAL.CPUx=0x2, is presented below:

  1. At power-up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold. The system continues to be held in this static state until all the internally regulated supplies have reached a safe operating state.
  2. The Power Manager (PM) starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal resets are maintained due to the external reset.
  3. The debugger generates at least 3 SWCLK clock cycles while RESET is asserted. RESET is then released, resulting in a debugger Cold-Plugging procedure.
  4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
  5. If x = 0 go to 6 otherwise go to 10.
  6. CPU 0 executes its Boot ROM.
  7. It is recommended to issue a chip-erase (supported by the Boot ROM) to ensure that the Flash is fully erased prior to programming.
  8. If the operation issued above was accepted and has completed successfully then DAL.CPU0 equals 0x2 therefore programming is available through the MEM-AP 0.
  9. After the operation is completed, the chip can be restarted either by asserting RESET, toggling power, or sending a command to the Boot ROM to jump to the NVM code. Make sure that the SWCLK clock is stopped while asserting RESET to prevent entering again the cold-plugging procedure.

    End of procedure for CPU 0.

  10. CPU1 executes its Boot ROM, DAL.CPU1 is updated during this process.
  11. If DAL.CPU1 is locked, unlock it using Boot ROM1 challenge/response features.
  12. If DAL.CPU1 equals 0x2 then programming is available through the MEM-AP 1.
  13. After the operation is completed, the chip can be restarted either by asserting RESET, toggling power, or sending a command to the Host Boot ROM to jump to the NVM code. Make sure that the SWCLK pin is high when releasing RESET to prevent entering again the cold-plugging procedure.

    End of procedure for CPU 1.