15.4 Peripheral Dependencies
| Peripheral Name | Base Address | NVIC IRQ Index: Source | MCLK AXI/APB Clocks Index:Name (1) | PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | Power Domain |
|---|---|---|---|---|---|
| PAC | 0x4481 0000 (APB B) | 35 : Peripheral Access Error (ERR) | AHB: MCLK.CLKMSK0[17] APB: MCLK.CLKMSK0[18] | 14 | VDDREG |
Note:
- Register Field: MCLK.CLKMSK{index/32}.MASK[index mod 32].
Debug Operation
When the CPU is halted in Debug mode, write protection of all peripherals is disabled and the PAC continues normal operation.
Register Access Protection
All registers with write access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:
- Write Control (WRCTRL) register
- AHB Client Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
- Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers
Optional write protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write Protection" property in each individual register description.
PAC write protection does not apply to accesses through an external debugger.