26.3 Block Diagram

As shown in the following figure, there are several power supply pins:

  • AVDD powers the Backup power domain as well as the ADCs, Analog Comparator (AC), and the Peripheral Touch Controller (PTC)
  • VDDREG powers the internal regulators for the VDDCORE_SW, VDDCORE_RAM, and VDDCORE_PLL power domains
  • VDDIO powers I/O lines, an External Crystal Oscillator (XOSC), the 48 MHz Digital Frequency Locked Loop (DFLL48), and three charge pumps which support the Analog Comparator (AC) and the ADCs on the device (ADC0-3 and PTC ADC). Most VDDIO pins also power the device's Flash panel via double bonding.
  • VDDUSB3V0 and VDDUSB3V1 power the USB ports on the device
Figure 26-1. Supply Controller Block Diagram

Power domains (PDs) shown above are not independent. VDDCORE_*, VDDIO, and VDDREG share the same ground, GND. But AVDD has its own ground, AVSS. AVDD and VDDIO inputs must share the same supply, VDD.

The block diagram above also shows a variety of internally regulated power domains (VDDCORE PDs), nominally at 1.2V:

  • VDDCORE_BU: Powers the backup domain. it contains peripherals that remain powered in the Backup Sleep mode
  • VDDCORE_SW: The main voltage domain for the CPU, bus, and most peripherals, which can be switch off (hence the _SW suffix)
  • VDDCORE_PLL: The domain for the high-speed clock PLL
  • VDDCORE_USB: Domain for the two USB ports
  • VDD_CORE_RAM: This domain is used to retain the devices SRAM

The device’s internal main voltage regulators have three different modes, controlled by the Supply Controller (SUPC):

  • Active Run Mode: The default mode when the CPU and peripherals are running
  • Idle/Standby: When the CPU and peripherals are in standby
  • Hibernate/Backup/Off Mode: When the chip is in backup mode, the internal regulator is off, the VDDCORE_SW core power domain is OFF. The VDDCORE_BU backup domain is powered by the backup regulator (Low Power Voltage Regulator for Core - LPVREGC).