26.2 Features

The SUPC controlled the following analog supply elements:

  • Voltage Regulator System
    • Main voltage regulators: LDO or Buck Converter in active, standby or hibernate mode (VREGSW0-3) Used for VDDCORE_SW domain.
    • Voltage regulator called VREGRAM used for VDDCORE_RAMX domain
    • Low Power voltage regulator in Backup Mode (LPVREGC)
    • Additional capless regulators for USB transceivers (VREGUSBn) and PLLs (VREGPLLn)
  • Voltage Reference System (Bandgap)
    • Reference voltage for ADC
    • Temperature sensor
    • Charge Pump for I/O pad and analog cells as PTC/AC/ADC in case of low VDD voltage
  • 3.3V Brown-Out Reset (BOR)
    • Two instances of BOR are used when calibrated to Monitor VDDIO/VDDA and VDDREG power supply voltages, during power up, active mode and standby sleep mode
    • Programmable threshold value loaded from NVM User Row at startup
    • Triggers resets
  • 3.3V Low Power Brown-Out Reset (DCBOR)
    • Used in Backup Mode to monitor VDDIO/VDDA and VDDREG
    • Threshold values loaded from NVM
    • Triggers resets
    • Operating modes: Continuous mode and Sampled Mode, (with programmable sampling frequency)
  • 1.2V PORCORE Detector
    • Monitors VDDcore power supply voltage
    • Tightly coupled with the capless regulator
    • Triggers resets
  • 3.3V Programmable Low voltage Detector
    • Monitors VDDREG
    • Configurable threshold and direction
    • Can trigger Interrupt
  • Output pins
    • Pin toggling on RTC event