34.7 Clocks

The PORT bus clock (CLK_PORT_APB) can be enabled and disabled in the Main Clock module, and the default state of CLK_PORT_APB can be found in the Peripheral Clock Masking section of the MCLK – Main Clock.

The PORT requires an APB clock, which may be divided from the CPU main clock and allows the CPU to access the registers of PORT through the high-speed matrix and the AHB/APB bridge.

The PORT also requires an AHB clock for CPU AHBP accesses to the PORT, which have a higher priority than the APB accesses in case of concurrent PORT accesses. That AHB clock is the internal PORT clock.