24.6.2.1 Initialization

The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRLA.ENABLE = 0):

  • The Operating Mode bits in the Control A register (CTRLA.MODE)
  • The Prescaler bits in the Control A register (CTRLA.PRESCALER)
  • The Clear on Match bit in the Control A register (CTRLA.MATCHCLR)
  • The Clock Representation bit in the Control A register (CTRLA.CLKREP)
  • The GP Registers Reset On Tamper Enable bit in the Control A register (CTRLA.GPTRST)

The following registers are enable-protected:

  • The Control B (CTRLB) register
  • The Event Control (EVCTRL) register
  • The Tamper Control (TAMPCTRL) register
  • The Tamper Control B (TAMPCTRLB) register

The Enable-protected bits and registers can be changed only when the RTC is disabled (CTRLA.ENABLE = 0). If the RTC is enabled (CTRLA.ENABLE = 1), these operations are necessary: first write CTRLA.ENABLE = 0 and check whether the write synchronization has finished, then change the desired bit field value. The Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'.

Enable-protection is denoted by the "Enable-Protected" property in the register description.

The RTC prescaler divides the source clock for the RTC counter.

Note: In Clock/Calendar mode, the prescaler must be configured to provide a 1 Hz clock to the counter for correct operation.

The frequency of the RTC clock (CLK_RTC_CNT) is given by the following formula:

CLK_RTC_CNT = [CLK_RTC / 2(PRESCALAR-1)] * (1 ± [((8192*128)+FREQCORR.VALUE) / (8192*128)])

The frequency of the oscillator clock, CLK_RTC_OSC, is given by fCLK_RTC_OSC, and fCLK_RTC_CNT is the frequency of the internal prescaled RTC clock, CLK_RTC_CNT.