29.5 Peripheral Dependencies
| Peripheral Name | EIC |
| Base Address | 0x4480 0000 (Peripheral Bus B) |
| NVIC IRQ Index:Source | NA : NMI 19-34: External Interrupt x (EXTINTx), x=0,1,…15 |
| MCLK AXI/APB Clocks Index:Name (1) | 16 : CLK_EIC_APB |
| GCLK Peripheral Channel Index:Clock Name (2) | 5 : GCLK_EIC |
| PAC Peripheral Peripheral Identifier (PAC.WRCTRL) | 13 |
| APB Mask Register[Index] | INTFLAGA[13] |
| AHB Mask Register[Index] | NA |
| EVSYS Users (EVSYS.USERm) | None |
| EVSYS Generators (EVSYS.CHANNELn) | 20-35 : External Interrupt x (EXTINTx), x=0,1,…15 |
| Power Domain | VDDREG |
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Note:
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I/O Lines
Using the EIC's I/O lines requires the I/O pins to be configured.
Power Management
All interrupts are available down to STANDBY sleep mode, but the EIC can be configured to automatically mask some interrupts in order to prevent device wake-up.
The EIC will continue to operate in any sleep mode where the selected source clock is running. The EIC's interrupts can be used to wake up the device from sleep modes. Events connected to the Event System can trigger other operations in the system without exiting sleep modes.
Clocks
The EIC bus clock (CLK EIC APB) can be enabled and disabled by the Main Clock Controller, the default state of CLK EIC APB can be found in the Peripheral Clock Masking section.
Some optional functions need a peripheral clock, which can either be a generic clock (GCLK EIC, for wider frequency selection) or an Ultra Low-Power 32 kHz clock (CLK ULP32K, for highest power efficiency). One of the clock sources must be configured and enabled before using the peripheral:
GCLK EIC is configured and enabled in the Generic Clock Controller.
CLK ULP32K is provided by the internal Ultra Low-Power (OSCULP32K) Oscillator in the OSC32KCTRL module.
Both GCLK EIC and CLK ULP32K are asynchronous to the user interface clock (CLK EIC APB). Due to the clock being asynchronous, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.
Interrupts
There are several interrupt request lines, at least one for the external interrupts (EXTINT) and one for non-maskable interrupt (NMI).
The EXTINT interrupt request line is connected to the interrupt controller. Using the EIC interrupt requires the interrupt controller to be configured first.
The NMI interrupt request line is also connected to the interrupt controller, but does not require the interrupt to be configured.
Events
The events are connected to the Event System. Using the events requires the Event System to be configured first.
Debug Operation
When the CPU is halted in debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for the following registers:
- Interrupt Flag Status and Clear register (INTFLAG)
- Non-Maskable Interrupt Flag Status and Clear register (NMIFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.