28.6.1 Basic Operation
Initialization
After a Power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the Reset source.
Enabling, Disabling, and Resetting
The RSTC module is always enabled.
Reset Causes and Effects
The latest Reset cause is available in the RCAUSE register and can be read during the application boot sequence to determine proper action.
The following are Reset source groups:
- Power supply Reset: Resets caused by an electrical issue. It covers POR Resets, (POR, PORCORE).
- Brown-out Reset: Resets caused by BORVDDx detectors.
- User Reset: Resets caused by the application. It covers external Resets (RESET pin), system Reset requests, CPU Lockup reset and watchdog Resets.
- Backup Reset: Reset cause when leaving Backup or Hibernate mode due to wake event (RTC).
The following table lists the parts of the device that are reset, depending on the reset type.
| Effect: Reset: | CPU Logic, Bus Logic | RTC(1), OSC32KCTRL
BKOUT, BOR(2), SUPC VREGCTRL & VREFCTRL(3) registers, CTRLA bits of PM | Flash Panel Controller,
OSC48M | Debug Logic | Other Modules |
|---|---|---|---|---|---|
| POR, PORCORE | Reset | Reset | Reset | Reset | Reset |
| External
Reset BORVDDx | Reset | No Reset | No Reset | Reset | Reset |
| WDT Reset Lockup Reset System Reset Request | Reset | No Reset | No Reset | No Reset | Reset |
| RTC | - | No Reset | Reset | Reset | - |
- RTC.DBGCTRL is reset in Backup Sleep mode.
- BOR register is retained during Backup mode and is not reset when exiting.
- VREGCTRL.VREGOUT is reset by User Reset so regulators go back to default setting.
The external Reset is generated when pulling the RESET pin low.
The POR, PORCORE, and BORVDDx (e.g: BORVDDA, BORVDDREG...) Reset sources are generated by the analog modules inside the PWR_SMOR or PWR_SMOR_DS controlled by the Supply Controller Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details refer to the “Arm® Cortex™ Technical Reference Manual”, available at www.arm.com).
The Lockup Reset is a Reset generated by the CPU when it enters a lockup state (for details refer to the “Arm® Cortex™ Technical Reference Manual”, available at www.arm.com).