29.4.1 CLB Software Input Register

The CLB Software Input (CLBSWINU:H:M:L) 8-bit registers form a 32-bit register (CLBSWIN) that can be used by user software to 'bit-bang' values into the CLB Look-up Tables (LUT). The CLB module can be programmed to use the bits from the CLBSWIN registers as inputs to the look-up tables (see Figure 29-3).

Note: The 32-bit CLBSWIN register is not directly user accessible. The CLBSWINU:H:M:L registers must be written individually.

CLBSWIN register synchronization occurs when the lower eight bits (CLBSWINL) are written by user software. When CLBSWINL is written, the contents of the all four registers are copied into holding latches, the CLBSWIN Register Input Busy (BUSY) bit is set (BUSY = '1'), and the CLBSWIN registers are locked and cannot be modified. Once synchronization is complete (1 BLE_clk cycle), module hardware clears the BUSY bit, and the CLBSWIN registers are unlocked and ready to be modified.

Important: The CLBSWINU, CLBSWINH, and CLBSWINM registers must be written prior to writing the CLBSWINL register, otherwise the current values in each respective register will be latched once CLBSWINL is written.