12.3 Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPHERAL) and the Main Clock (GCLK_MAIN) can be seen in the figure below.
Note: 1. If GENCTRL.SRC=0x01(GCLKIN), the
GCLK_IO is set as an input.
The generation of Peripheral Clock signals (GCLK_PERIPHERAL) and the Main Clock (GCLK_MAIN) can be seen in the figure below.
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