8.1.1 Cortex M0+ Configuration
Features | Configurable Option | Device Configuration |
---|---|---|
Interrupts | External interrupts 0-32 | 28 |
Data Endianness | Little-endian or big-endian | Little-endian |
SysTick Timer | Present or absent | Present |
Number of Watchpoint Comparators | 0, 1, 2 | 2 |
Number of Breakpoint Comparators | 0, 1, 2, 3, 4 | 4 |
Halting Debug Support | Present or absent | Present |
Multiplier | Fast or small | Fast (single cycle) |
Single-Cycle I/O Port | Present or absent | Present |
Wake-up Interrupt Controller | Supported or not supported | Not supported |
Vector Table Offset Register | Present or absent | Present |
Unprivileged/Privileged Support | Present or absent | Absent(1) |
Memory Protection Unit | Not present or 8-region | Not present |
Reset all Registers | Present or absent | Absent |
Instruction Fetch Width | 16-bit only or mostly 32-bit | 32-bit |
Note:
- All software run in Privileged mode only.
The ARM Cortex-M0+ core has the following two bus interfaces:
- Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system memory, which includes Flash and RAM.
- Single 32-bit I/O port bus interfacing to the port with 1-cycle loads and stores.