10.13.1 Control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRL |
| Offset: | 0x0000 |
| Reset: | 0x00 |
| Property: | PAC Write Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Reserved | Reserved | CE | MBIST | SWRST | |||||
| Access | - | - | W | W | W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – Reserved Must be set to 0.
Bit 6 – Reserved Must be set to 0.
Bit 4 – CE Chip Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the chip erase
operation.
Bit 3 – MBIST Memory Built-In Self-Test
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the memory BIST
algorithm.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the module.
