29.5.3 Clocks

The DAC bus clock (CLK_DAC_APB) can be enabled and disabled by the power manager, and the default state of CLK_DAC_APB can be found in the Peripheral Clock Masking section.

A generic clock (GCLK_DAC) is required to clock the DAC controller. This clock must be configured and enabled in the generic clock controller before using the DAC controller. Refer to GCLK – Generic Clock Controller for details.

This generic clock is asynchronous to the bus clock (CLK_DAC_APB). Due to this asynchronicity, writes to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.