16.3.2 CCL Pin Position
| Name: | CCLROUTEA |
| Offset: | 0x01 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LUT3 | LUT2 | LUT1 | LUT0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 3 – LUT3 CCL LUT 3 Signals
This bit field controls the pin locations for CCL LUT 3 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0x0 | DEFAULT | PC4 | PC0 | PC1 | PC2 |
0x1 | ALT1 | PA5 | PC0 | PC1 | PC2 |
Bit 2 – LUT2 CCL LUT 2 Signals
This bit field controls the pin locations for CCL LUT 2 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0x0 | DEFAULT | PB3 | PB0 | PB1 | PB2 |
0x1 | ALT1 | PB6 | PB0 | PB1 | PB2 |
Bit 1 – LUT1 CCL LUT 1 Signals
This bit field controls the pin locations for CCL LUT 1 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0x0 | DEFAULT | PA7 | PC3 | PC4 | PC5 |
0x1 | ALT1 | PC1 | PC3 | PC4 | PC5 |
Bit 0 – LUT0 CCL LUT 0 Signals
This bit field controls the pin locations for CCL LUT 0 signals.
| Value | Name | Description | |||
|---|---|---|---|---|---|
| OUT | IN0 | IN1 | IN2 | ||
0x0 | DEFAULT | PA4 | PA0 | PA1 | PA2 |
0x1 | ALT1 | PB4 | PA0 | PA1 | PA2 |