32.7 Register Summary - EUSART
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0x070B | Reserved | |||||||||
| 0x070C | RC1REG | 7:0 | RCREG[7:0] | |||||||
| 0x070D | TX1REG | 7:0 | TXREG[7:0] | |||||||
| 0x070E | SP1BRG | 7:0 | SPBRG[7:0] | |||||||
| 15:8 | SPBRG[15:8] | |||||||||
| 0x0710 | RC1STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x0711 | TX1STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x0712 | BAUD1CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||
0x0713 ... 0x0715 | Reserved | |||||||||
| 0x0716 | RC2REG | 7:0 | RCREG[7:0] | |||||||
| 0x0717 | TX2REG | 7:0 | TXREG[7:0] | |||||||
| 0x0718 | SP2BRG | 7:0 | SPBRG[7:0] | |||||||
| 15:8 | SPBRG[15:8] | |||||||||
| 0x071A | RC2STA | 7:0 | SPEN | RX9 | SREN | CREN | ADDEN | FERR | OERR | RX9D |
| 0x071B | TX2STA | 7:0 | CSRC | TX9 | TXEN | SYNC | SENDB | BRGH | TRMT | TX9D |
| 0x071C | BAUD2CON | 7:0 | ABDOVF | RCIDL | SCKP | BRG16 | WUE | ABDEN | ||