1 Pin Descriptions


Pin Number	Pin Name	Pin Function
1	nINTO	Active low, open-drain interrupt output.
2	nRSTO	Active low, open-drain reset output.
3	SGND	Signal ground. Connect to reference ground plane.
4	SVIN	Input voltage for the analog control circuitry. Decouple SVIN to SGND with a 1μF (minimum) ceramic capacitor.
5	SDA	I²C interface serial data.
6	SCL	I²C interface serial clock.
7	nSTRTO	Active low, open-drain START event output. The nSTRTO signal is asserted LOW whenever the EN is detected to be HIGH.
8	PWRHLD	Power hold input. Typically asserted high by the MPU to maintain power after the initial startup triggered by EN. PWRHLD will be asserted low by the MPU to initiate a PMIC shutdown sequence.
9	OUT1	Output sensing for buck channel 1. Connect to the regulation point for V_OUT1.
10	PVIN1	Power input voltage of buck channel 1. Connect a ceramic capacitor from PVIN1 to ground, to localize pulsed currents loops and decouple switching noise.
11	SW1	Switch node of buck channel 1. Internal power MOSFET switches and external inductor connection.
12	VSET1	Connect a resistor on this pin to ground to define the start-up voltage of the buck channel 1.
13	VSET2	Connect a resistor on this pin to ground to define the start-up voltage of the buck channel 2
14	SW2	Switch node of buck channel 2. Internal power MOSFET switches and external inductor connection.
15	PVIN2	Power input voltage of buck channel 2. Connect a ceramic capacitor from PVIN2 to ground, to localize pulsed currents loops and decouple switching noise.
16	OUT2	Output sensing for buck channel 2. Connect to the regulation point for V_OUT2.
17	VSETL2	Connect a resistor on this pin to ground to define the start-up voltage of the LDO2.
18	VSETL1	Connect a resistor on this pin to ground to define the start-up voltage of the LDO1.
19	LOUT1	LDO1 output. Decouple LOUT1 to ground with a 2.2μF (minimum) ceramic capacitor.
20	LVIN	Input voltage for LDO1 and LDO2. Decouple LVIN to ground with a 2.2μF (minimum) ceramic capacitor.
21	LOUT2	LDO2 output. If LDO2 is in use, decouple LOUT2 to SGND with a 2.2μF (minimum) ceramic capacitor.
22	LPM	Low-power mode input pin. In combination with PWRHLD and HPM, this pin defines the power mode status of the MCP16503.
23	HPM	High-performance mode input pin. In combination with PWRHLD and LPM, this pin defines the power mode status of the MCP16503. Connect to ground if not used.
24	EN	Enable input. Drive EN high to initiate a start-up sequence at power up or after a power down triggered by EN.
25	OUT3	Output sensing for buck channel 3. Connect to the regulation point for V_OUT3.
26	PVIN3	Power input voltage of buck channel 3. Connect a ceramic capacitor from PVIN3 to ground, to localize pulsed currents loops and decouple switching noise.
27	SW3	Switch node of buck channel 3. Internal power MOSFET switches and external inductor connection.
28	VSET3	Connect a resistor on this pin to ground to define the start-up voltage of the buck channel 3.
29	VSET4	Connect a resistor on this pin to ground to define the start-up voltage of the buck channel 4.
30	SW4	Switch node of buck channel 4. Internal power MOSFET switches and external inductor connection.
31	PVIN4	Power input voltage of buck channel 4. Connect a ceramic capacitor from PVIN4 to ground, to localize pulsed currents loops and decouple switching noise.
32	OUT4	Output sensing for buck channel 4. Connect to the regulation point for V_OUT4.
—	EP	Exposed pad (ePad). Connect to ground plane with vias to ensure good thermal properties.

Note: The PVINx pins, SVIN pin and the LVIN pin shall be supplied from the same input voltage rail.