12.3.2 Writing to DFM

To write a DFM location, the address must first be written to the NVMADR register and the data written to the NVMDATL register. The sequence shown in NVM Unlock Sequence must be followed to initiate the write cycle. Block writes, also referred to as sector writes, are not supported for the DFM.

The write will not begin if NVM Unlock sequence is not exactly followed for each byte. It is strongly recommended that interrupts be disabled during this code segment.

Additionally, the NVMEN bit must be set to enable NVM control. This mechanism prevents accidental writes to DFM due to unexpected code execution (i.e., runaway programs). The NVMEN bit should be kept clear at all times, except when updating the DFM. The NVMEN bit is not cleared by hardware.

After a write sequence has been initiated, NVMCON1, NVMADR and NVMDAT cannot be modified. The WR bit will be inhibited from being set unless the NVMEN bit is set.

After a write sequence has been initiated, clearing the NVMEN bit will not affect this write cycle. A single DFM byte is written and the operation includes an implicit erase cycle for that word. CPU execution continues in parallel and at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The user can either enable this interrupt or poll this bit. NVMIF must be cleared by software.

; Data Flash Memory Address to write
        MOVF    DFM_ADDRL, W        ;
        MOVWF   NVMADRL             ; Setup Address low byte
        MOVF    DFM_ADDRH, W        ;
        MOVWF   NVMADRH             ; Setup Address high byte
        MOVF    DFM_ADDRU, W        ;
        MOVWF   NVMADRU             ; Setup Address upper byte
; Data Memory Value to write
        MOVF    DMF_DATA, W         ;
        MOVWF   NVMDATL             ;
; Enable writes
        BSF     NVMCON0, NVMEN      ; Enable NVM
; Disable interrupts
        BCF     INTCON, GIE         ;
; –------- Required Sequence –--------
        MOVLW   55h                 ;
        MOVWF   NVMCON2             ;
        MOVLW   AAh                 ;
        MOVWF   NVMCON2             ;
        BSF     NVMCON1, WR         ; Set WR bit to begin write
; –------------------------------------
; Wait for write to complete 
        BTFSC   NVMCON1, WR         ; DFM writes do not stall the CPU
        BRA     $-2
; Enable INT
        BSF     INTCON, GIE         ;
; Disable writes
        BCF     NVMCON0, NVMEN      ;