1.3 Details on Individual Family Members

Devices in the PIC18F24/25Q10 family are available in 28-pin packages. The block diagram for this device is shown in Figure 1-1.

The devices have the following differences:

  1. Program Flash Memory
  2. Data Memory SRAM
  3. Data Memory EEPROM
  4. A/D channels
  5. I/O ports
  6. Enhanced USART
  7. Input Voltage Range/Power Consumption

All other features for devices in this family are identical. These are summarized in the following Device Features table.

The pinouts for all devices are listed in the pin summary tables.

Table 1-1. Device Features
Features PIC18F24Q10 PIC18F25Q10
Program Memory (Bytes)

16384

32768
Program Memory (Instructions)

8192

16384
Data Memory (Bytes)

1024

2048
Data EEPROM Memory (Bytes)

256

256
I/O Ports A,B,C,E(1)

A,B,C,E(1)
Capture/Compare/PWM Modules (CCP) 2 2
10-Bit Pulse-Width Modulator (PWM) 2 2
10-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator 4 internal

24 external

 4 internal

24 external
Packages

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin VQFN

28-pin SPDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

28-pin VQFN
Interrupt Sources 36
Timers (16-/8-bit) 4/3
Serial Communications 1 MSSP,

1 EUSART
Enhanced Complementary Waveform Generator (ECWG) 1
Zero-Cross Detect (ZCD) 1
Data Signal Modulator (DSM) 1
Peripheral Pin Select (PPS) Yes
Peripheral Module Disable (PMD) Yes
16-bit CRC with NVMSCAN Yes
Programmable High/Low-Voltage Detect (HLVD) Yes
Programmable Brown-out Reset (BOR) Yes
Resets (and Delays) POR, BOR,

RESET Instruction,

Stack Overflow,

Stack Underflow

(PWRT, OST),

MCLR, WDT
Instruction Set 75 Instructions;

83 with Extended Instruction Set enabled
Operating Frequency DC – 64 MHz
Note 1: PORTE contains the single RE3 read-only bit.
Figure 1-1. PIC18F24/25Q10 Family Block Diagram