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28-Pin, Low-Power, High-Performance Microcontrollers
Description
Core Features
Memory
Operating Characteristics
Power-Saving Operation Modes
Digital Peripherals
Analog Peripherals
Clocking Structure
Programming/Debug Features
PIC18F24/25Q10 Family Types
Packages
Pin Diagrams
Pin Allocation Tables
1 Device Overview
1.1 New Core Features
1.2 Other Special Features
1.3 Details on Individual Family Members
1.4 Register and Bit Naming Conventions
1.5 Register Legend
2 Guidelines for Getting Started with PIC18F24/25Q10 Microcontrollers
2.1 Basic Connection Requirements
2.2 Power Supply Pins
2.3 Master Clear (MCLR) Pin
2.4 In-Circuit Serial Programming™ (ICSP™) Pins
2.5 External Oscillator Pins
2.6 Unused I/Os
3 Device Configuration
3.1 Configuration Words
3.2 Code Protection
3.3 Write Protection
3.4 User ID
3.5 Device ID and Revision ID
3.6 Register Summary - Configuration Words
3.7 Register Definitions: Configuration Words
3.8 Register Summary - Device and Revision
3.9 Register Definitions: Device and Revision
4 OSC - Oscillator Module
4.1 Overview
4.2 Clock Source Types
4.3 Clock Switching
4.4 Fail-Safe Clock Monitor
4.5 Register Summary - OSC
4.6 Register Definitions: Oscillator Control
5 Reference Clock Output Module
5.1 Clock Source
5.2 Programmable Clock Divider
5.3 Selectable Duty Cycle
5.4 Operation in Sleep Mode
5.5 Register Summary: Reference CLK
5.6 Register Definitions: Reference Clock
6 Power-Saving Operation Modes
6.1 Doze Mode
6.2 Sleep Mode
6.3 Idle Mode
6.4 Peripheral Operation in Power-Saving Modes
6.5 Register Summary - Power Savings Control
6.6 Register Definitions: Power Savings Control
7 (PMD) Peripheral Module Disable
7.1 Disabling a Module
7.2 Enabling a Module
7.3 Register Summary - PMD
7.4 Register Definitions: Peripheral Module Disable
8 Resets
8.1 Power-on Reset (POR)
8.2 Brown-out Reset (BOR)
8.3 Low-Power Brown-out Reset (LPBOR)
8.4 MCLR Reset
8.5 Windowed Watchdog Timer (WWDT) Reset
8.6 RESET Instruction
8.7 Stack Overflow/Underflow Reset
8.8 Programming Mode Exit
8.9 Power-up Timer (PWRT)
8.10 Start-up Sequence
8.11 Determining the Cause of a Reset
8.12 Power Control (PCON0) Register
8.13 Register Summary - BOR Control and Power Control
8.14 Register Definitions: Power Control
9 (WWDT) Windowed Watchdog Timer
9.1 Independent Clock Source
9.2 WWDT Operating Modes
9.3 Time-out Period
9.4 Watchdog Window
9.5 Clearing the WWDT
9.6 Operation During Sleep
9.7 Register Summary - WDT Control
9.8 Register Definitions: Windowed Watchdog Timer Control
10 Memory Organization
10.1 Program Memory Organization
10.2 PIC18 Instruction Cycle
10.3 Data Memory Organization
10.4 Data Addressing Modes
10.5 Data Memory and the Extended Instruction Set
10.6 PIC18 Instruction Execution and the Extended Instruction Set
10.7 Register Summary: Memory and Status
10.8 Register Definitions: Memory and Status
11 (NVM) Nonvolatile Memory Control
11.1 Program Flash Memory
11.2 User ID, Device ID and Configuration Word Access
11.3 Data Flash Memory (DFM)
11.4 Register Summary: NVM Control
11.5 Register Definitions: Nonvolatile Memory
12 8x8 Hardware Multiplier
12.1 Introduction
12.2 Operation
12.3 Register Summary - 8x8 Hardware Multiplier
12.4 Register Definitions: 8x8 Hardware Multiplier
13 (CRC) Cyclic Redundancy Check Module with Memory Scanner
13.1 CRC Module Overview
13.2 CRC Functional Overview
13.3 CRC Polynomial Implementation
13.4 CRC Data Sources
13.5 CRC Check Value
13.6 CRC Interrupt
13.7 Configuring the CRC
13.8 Program Memory Scan Configuration
13.9 Scanner Interrupt
13.10 Scanning Modes
13.11 Register Summary - CRC
13.12 Register Definitions: CRC and Scanner Control
14 Interrupts
14.1 Midrange Compatibility
14.2 Interrupt Priority
14.3 Interrupt Response
14.4 INTCON Registers
14.5 PIR Registers
14.6 PIE Registers
14.7 IPR Registers
14.8 INTn Pin Interrupts
14.9 TMR0 Interrupt
14.10 Interrupt-on-Change
14.11 Context Saving During Interrupts
14.12 Register Summary - Interrupt Control
14.13 Register Definitions: Interrupt Control
15 I/O Ports
15.1 I/O Priorities
15.2 PORTx Registers
15.3 PORTE Registers
15.4 Register Summary - Input/Output
15.5 Register Definitions: Port Control
16 Interrupt-on-Change
16.1 Features
16.2 Overview
16.3 Block Diagram
16.4 Enabling the Module
16.5 Individual Pin Configuration
16.6 Interrupt Flags
16.7 Clearing Interrupt Flags
16.8 Operation in Sleep
16.9 Register Summary - Interrupt-on-Change
16.10 Register Definitions: Interrupt-on-Change Control
17 (PPS) Peripheral Pin Select Module
17.1 PPS Inputs
17.2 PPS Outputs
17.3 Bidirectional Pins
17.4 PPS Lock
17.5 PPS One-Way Lock
17.6 Operation During Sleep
17.7 Effects of a Reset
17.8 Register Summary - PPS
17.9 Register Definitions: PPS Input and Output Selection
18 Timer0 Module
18.1 Timer0 Operation
18.2 Clock Selection
18.3 Timer0 Output and Interrupt
18.4 Operation During Sleep
18.5 Register Summary - Timer0
18.6 Register Definitions: Timer0 Control
19 Timer1 Module with Gate Control
19.1 Timer1 Operation
19.2 Clock Source Selection
19.3 Timer1 Prescaler
19.4 Secondary Oscillator
19.5 Timer1 Operation in Asynchronous Counter Mode
19.6 Timer1 16-Bit Read/Write Mode
19.7 Timer1 Gate
19.8 Timer1 Interrupt
19.9 Timer1 Operation During Sleep
19.10 CCP Capture/Compare Time Base
19.11 CCP Special Event Trigger
19.12 Peripheral Module Disable
19.13 Register Summary - Timer1
19.14 Register Definitions: Timer1
20 Timer2 Module
20.1 Timer2 Operation
20.2 Timer2 Output
20.3 External Reset Sources
20.4 Timer2 Interrupt
20.5 Operating Modes
20.6 Operation Examples
20.7 Timer2 Operation During Sleep
20.8 Register Summary - Timer2
20.9 Register Definitions: Timer2 Control
21 Capture/Compare/PWM Module
21.1 CCP Module Configuration
21.2 Capture Mode
21.3 Compare Mode
21.4 PWM Overview
21.5 Register Summary - CCP Control
21.6 Register Definitions: CCP Control
22 (PWM) Pulse-Width Modulation
22.1 Fundamental Operation
22.2 PWM Output Polarity
22.3 PWM Period
22.4 PWM Duty Cycle
22.5 PWM Resolution
22.6 Operation in Sleep Mode
22.7 Changes in System Clock Frequency
22.8 Effects of Reset
22.9 Setup for PWM Operation using PWMx Output Pins
22.10 Setup for PWM Operation to Other Device Peripherals
22.11 Register Summary - Registers Associated with PWM
22.12 Register Definitions: PWM Control
23 ZCD - Zero-Cross Detection Module
23.1 External Resistor Selection
23.2 ZCD Logic Output
23.3 ZCD Logic Polarity
23.4 ZCD Interrupts
23.5 Correction for ZCPINV Offset
23.6 Handling VPEAK Variations
23.7 Operation During Sleep
23.8 Effects of a Reset
23.9 Disabling the ZCD Module
23.10 Register Summary: ZCD Control
23.11 Register Definitions: ZCD Control
24 (CWG) Complementary Waveform Generator Module
24.1 Fundamental Operation
24.2 Operating Modes
24.3 Start-up Considerations
24.4 Clock Source
24.5 Selectable Input Sources
24.6 Output Control
24.7 Dead-Band Control
24.8 Rising Edge and Reverse Dead Band
24.9 Falling Edge and Forward Dead Band
24.10 Dead-Band Jitter
24.11 Auto-Shutdown
24.12 Operation During Sleep
24.13 Configuring the CWG
24.14 Register Summary - CWG Control
24.15 Register Definitions: CWG Control
25 (DSM) Data Signal Modulator Module
25.1 DSM Operation
25.2 Modulator Signal Sources
25.3 Carrier Signal Sources
25.4 Carrier Synchronization
25.5 Carrier Source Polarity Select
25.6 Programmable Modulator Data
25.7 Modulated Output Polarity
25.8 Operation in Sleep Mode
25.9 Effects of a Reset
25.10 Peripheral Module Disable
25.11 Register Summary - DSM
25.12 Register Definitions: Modulation Control
26 MSSP - Master Synchronous Serial Port Module
26.1 SPI Mode Overview
26.2 SPI Mode Operation
26.3 I2C Mode Overview
26.4 I2C Mode Operation
26.5 I2C Client Mode Operation
26.6 I2C Host Mode
26.7 Baud Rate Generator
26.8 Register Summary - MSSP Control
26.9 Register Definitions: MSSP Control
27 EUSART - Enhanced Universal Synchronous Asynchronous Receiver Transmitter
27.1 EUSART Asynchronous Mode
27.2 EUSART Baud Rate Generator (BRG)
27.3 EUSART Synchronous Mode
27.4 EUSART Operation During Sleep
27.5 Register Summary - EUSART
27.6 Register Definitions: EUSART Control
28 (FVR) Fixed Voltage Reference
28.1 Independent Gain Amplifiers
28.2 FVR Stabilization Period
28.3 Register Summary - FVR
28.4 Register Definitions: FVR Control
29 Temperature Indicator Module
29.1 Circuit Operation
29.2 Minimum Operating VDD
29.3 Temperature Output
29.4 ADC Acquisition Time
30 (DAC) 5-Bit Digital-to-Analog Converter Module
30.1 Output Voltage Selection
30.2 Ratiometric Output Level
30.3 DAC Voltage Reference Output
30.4 Operation During Sleep
30.5 Effects of a Reset
30.6 Register Summary - DAC Control
30.7 Register Definitions: DAC Control
31 (ADC2) Analog-to-Digital Converter with Computation Module
31.1 ADC Configuration
31.2 ADC Operation
31.3 ADC Acquisition Requirements
31.4 Capacitive Voltage Divider (CVD) Features
31.5 Computation Operation
31.6 Register Summary - ADC Control
31.7 Register Definitions: ADC Control
32 CMP - Comparator Module
32.1 Comparator Overview
32.2 Comparator Control
32.3 Comparator Hysteresis
32.4 Operation With Timer1 Gate
32.5 Comparator Interrupt
32.6 Comparator Positive Input Selection
32.7 Comparator Negative Input Selection
32.8 Comparator Response Time
32.9 Analog Input Connection Considerations
32.10 CWG1 Auto-Shutdown Source
32.11 ADC Auto-Trigger Source
32.12 Even Numbered Timers Reset
32.13 Operation in Sleep Mode
32.14 Register Summary - Comparator
32.15 Register Definitions: Comparator Control
33 HLVD - High/Low-Voltage Detect
33.1 Operation
33.2 Setup
33.3 Current Consumption
33.4 HLVD Start-up Time
33.5 Applications
33.6 Operation During Sleep
33.7 Operation During Idle and Doze Modes
33.8 Effects of a Reset
33.9 Register Summary - HLVD
33.10 Register Definitions: HLVD Control
34 Register Summary
35 In-Circuit Serial Programming™ (ICSP™)
35.1 High-Voltage Programming Entry Mode
35.2 Low-Voltage Programming Entry Mode
35.3 Common Programming Interfaces
36 Instruction Set Summary
36.1 Standard Instruction Set
36.2 Extended Instruction Set
37 Development Support
37.1 MPLAB X Integrated Development Environment Software
37.2 MPLAB XC Compilers
37.3 MPASM Assembler
37.4 MPLINK Object Linker/MPLIB Object Librarian
37.5 MPLAB Assembler, Linker and Librarian for Various Device Families
37.6 MPLAB X SIM Software Simulator
37.7 MPLAB REAL ICE In-Circuit Emulator System
37.8 MPLAB ICD 3 In-Circuit Debugger System
37.9 PICkit 3 In-Circuit Debugger/Programmer
37.10 MPLAB PM3 Device Programmer
37.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits
37.12 Third-Party Development Tools
38 Electrical Specifications
38.1 Absolute Maximum Ratings(†)
38.2 Standard Operating Conditions
38.3 DC Characteristics
38.4 AC Characteristics
39 DC and AC Characteristics Graphs and Tables
39.1 Analog to Digital Converter Oscillator Graphs
39.2 Analog-to-Digital Converter (10-bit) Graphs
39.3 Bandgap Ready Graphs
39.4 Brown Out Reset Graphs
39.5 Comparator Graphs
39.6 Fixed Voltage Reference Graphs
39.7 I/O Rise/Fall Times Graphs
39.8 IDD Graphs
39.9 Input Buffer Graphs
39.10 IPD Graphs
39.11 HFINTOSC Wake From Sleep Graphs
39.12 LFINTOSC Wake From Sleep Graphs
39.13 Low Power Brown-Out Reset Graphs
39.14 Low-Voltage Detect Graphs
39.15 OSCTUNE Graphs
39.16 Power On Reset Graphs
39.17 Power-Up Timer Graphs
39.18 Temperature Indicator Graphs
39.19 VOH - VOL Graphs
39.20 Watchdog Timer Graphs
39.21 Weak Pull Up Graphs
39.22 Zero Cross Detection Graphs
40 Packaging Information
40.1 Package Details
41 Appendix A: Revision History
Microchip Information
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