1.1.1 PolarFire/PolarFire SoC – Change to Default Settings of Specific Unused I/O Pins

Prior to Libero SoC v2021.3, programmed I/O defaults in PolarFire/PolarFire SoC designs for a specific subset of unused I/O pins would glitch at power up. (In this context, the fabric is programmed, but the I/Os are unused in the design.) If impacted I/O pins are connected on system, the PCB designer should be aware that they can glitch using Libero SoC-generated defaults. Such designs will get updated to the corrected new default setting if the Generate FPGA Array data tool is rerun in Libero SoC v2021.3 or later.