1.1.2 RTG4 – MSIO/MSIOD Input IOPAD Timing Update

When the Libero SoC project-level SET mitigation setting is disabled, RTG4 MSIO and MSIOD input buffer delays have been updated to reflect the silicon behavior which, in the case of MSIO and MSIOD, are always mitigated regardless of the SET mitigation setting.

The impact of this timing update on the internal regression suite of designs does not show any occurrence of new violations. The maximum performance degradation is well below our built-in timing model margin compared to the actual silicon performance.