1.4.1.5 PolarFire XCVR-Sourced Fabric Clocks and Jitter Compensation

The PolarFire XCVR can source three different clocks into the fabric:

  • TX_CLK
  • RX_CLK
  • REFCLK (FAB_REF_CLK)

These clocks contain high-frequency jitter that is not automatically considered by Libero in the timing report and SmartTime. It is recommended that users add clock-uncertainty constraints to these clocks in their design. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.

Table 1-3. Recommended Values for Clock Uncertainty
Clock TypeSTD-1
FAB_REF_CLK on Global275 ps200 ps
FAB_REF_CLK on RegionalN/AN/A
TX_CLK_G on Global300 ps225 ps
TX_CLK_R on Regional225 ps150 ps
RX_CLK_G on Global325 ps250 ps
RX_CLK_R on Regional250 ps175 ps
The following example shows a clock-uncertainty constraint that uses a -1 speed grade.
set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
 
set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_R } ]

The following example shows a clock-uncertainty constraint with STD speed grade.


# TX_CLK and RX_CLK on Globals
 
set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
 
set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_G } ]
 
# FAB_REF_CLK on Global
 
set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]

The automatic management of these constraints will be added in a future release of Libero SoC.

Note: It is also important to add the other required jitter sources as clock uncertainty into your design constraints. See the datasheet for the jitter to be added for components such as PLL, DLL, and RC Oscillator. For input pins that are direct or are inputs to the DLL (but not for a PLL), the input jitter on the clock input pin must also be added to your timing constraints.