29.4.2 Timer Counter and Capture Registers
To read the raw counter value using the TUxyTMR counter register, the RDSEL bit must be set. When the timer is running in either Synchronous or Asynchronous mode, directly reading the TUxyTMR counter register can produce erroneous values. This can occur when the counter/timer is operating from an asynchronous clock source or when the read happens coincidentally with the rollover of the bottom 8 bits of the TUxyTMR counter register.
Clearing the RDSEL bit directs all counter/timer reads through the TUxyCR capture register. The TUxyCR capture register is functionally a read-only register and is loaded directly from the counter/timer in response to either of the following three conditions:
- Setting the CAPT command bit.
- When a stop event is generated.
- In the event of an ERS rising edge (or falling edge based on EPOL bit selection) if the Stop condition is set to none. See Stop Event for more details on Stop condition.
In the event of an ERS rising capture, the TUxyCR capture register must be read before the event of a second ERS rising or the data captured will be overwritten by the second rising event.
ON Bit | CSYNC Bit | Behavior of CAPT and CLR Commands |
---|---|---|
1 (Timer Running) |
1 |
Synchronization delay of three timer clock cycles applies before the desired action is performed |
1 (Timer Running) |
0 |
No synchronization delay applies. Desired action is performed immediately. |
0 (Timer Stopped) |
1 |
Synchronization delay of three timer clock cycles applies. The desired action is delayed until timer clock resumes. |
0 (Timer Stopped) |
0 |
No synchronization delay applies. Desired action is performed immediately. |
- Reading and writing the
TUxyTMR counter register when the timer is running (ON =
1
) is not recommended. The TUxyTMR counter register needs to be read or written to only when the timer is stopped (ON =0
) to prevent data corruption. - The TUxyTMR register, like many othe registers in the module, remains unchanged after a non-POR/BOR system Reset. It is recommended to always clear this register at the start of program execution to avoid counting from an unknown value.
- Setting the CLR bit does not reset the TUxyCR capture register.
- The TUxyTMR register needs to not be written as a means to change the effective period. If the intention is to change the timer period, the TUxyPR period register needs to be changed instead. See Timer Period Register for more details on how to change the timer period while the timer is running.
- When software sets a CLR or
CAPT command bit, the bit value of ‘
1
’ is indicated in the SFR immediately, to indicate that the over-and-back clock synchronization is not complete. However, a sufficiently high timer clock frequency might complete the cross-domain synchronization within one instruction cycle and the bit value would always appear to be ‘0
’. - Setting CLR or CAPT command
bits to ‘
0
’ has no effect. - The timer starts counting by
incrementing the TUxyTMR value to the next valid counter value. For
instance, if the counter is in Reset state (TUxyTMR =
0
), then the timer starts counting from 1. If the TUxyTMR = PR and RESET = at PR Match, then the timer will start counting by resetting the counter to zero first.