37.5.3 I2CxCON2
| Name: | I2CxCON2 |
| Address: | 0x0295 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ACNT | GCEN | ABD | SDAHT[1:0] | BFRET[1:0] | |||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 7 – ACNT Auto-Load I2C Count Register Enable
| Value | Description |
|---|---|
1 |
The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register |
0 |
Auto-load of I2CxCNT is disabled |
Bit 6 – GCEN
General Call Address Enable (used when MODE = 00x or MODE =
11x)
| Value | Description |
|---|---|
1 |
General
Call Address (0x00) causes an address match
event |
0 |
General Call addressing is disabled |
Bit 4 – ABD Address Buffer Disable
Bits 3:2 – SDAHT[1:0] SDA Hold Time Selection
| Value | Description |
|---|---|
11 |
No additional hold time on SDA after falling edge of SCL |
10 |
Minimum of 30 ns hold time on SDA after the falling SCL edge |
01 |
Minimum of 100 ns hold time on SDA after the falling SCL edge |
00 |
Minimum of 300 ns hold time on SDA after the falling SCL edge |
Bits 1:0 – BFRET[1:0] Bus Free Time Selection
| Value | Description |
|---|---|
11 |
64 baud-divided I2CxCLK pulses |
10 |
32 baud-divided I2CxCLK pulses |
01 |
16 baud-divided I2CxCLK pulses |
00 |
8 baud-divided I2CxCLK pulses |