3.7.3 Signal Description
| Name | Description | Type | Active Level |
|---|---|---|---|
| SDCK | SDRAM Clock | Output | – |
| SDCKE | SDRAM Clock Enable | Output | High |
| SDCS | SDRAMC Chip Select | Output | Low |
| BA[1:0] | Bank Select Signals | Output | – |
| RAS | Row Signal | Output | Low |
| CAS | Column Signal | Output | Low |
| SDWE | SDRAM Write Enable | Output | Low |
| NBS[3:0] | Data Mask Enable Signals | Output | Low |
| SDRAMC_A[12:0] | Address Bus | Output | – |
| D[31:0] | Data Bus | I/O | – |