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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
3
Memories
3.7
SDRAM Controller (SDRAMC)
3.7.6
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.7
SDRAM Controller (SDRAMC)
3.7.1
Description
3.7.2
Embedded Characteristics
3.7.3
Signal Description
3.7.4
Software Interface/SDRAM Organization, Address Mapping
3.7.5
Product Dependencies
3.7.6
Functional Description
3.7.6.1
SDRAM Controller Write Cycle
3.7.6.2
SDRAM Controller Read Cycle
3.7.6.3
Border Management
3.7.6.4
SDRAM Controller Refresh Cycles
3.7.6.5
Power Management
3.7.6.6
Scrambling/Unscrambling Function
3.7.6.7
Clearing Scrambling Keys on Tamper Event
3.7.6.8
Interface with Multiplexed Data/Address Lines and Data/Address/Command Lines
3.7.6.9
Register Write Protection
3.7.6.10
Security and Safety Analysis and Reports
3.7.7
Register Summary
3.8
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.7.6 Functional Description
