3.2.5.1 Hardware Interface

The following table details the connections to be applied between the EBI pins and the external devices for each memory controller.

Table 3-3. EBI Pins and External Static Device Connections
Signals: EBI_	Pins of the Interfaced Device
Signals: EBI_	8-bit  Static Device	2 x 8-bit  Static Devices	16-bit  Static Device	4 x 8-bit  Static Devices	2 x 16-bit  Static Devices	32-bit  Static Device
Controller	SMC
D[7:0]	D[7:0]	D[7:0]	D[7:0]	D[7:0]	D[7:0]	D[7:0]
D[15:8]	–	D[15:8]	D[15:8]	D[15:8]	D[15:8]	D[15:8]
D[23:16]	–	–	–	D[23:16]	D[23:16]	D[23:16]
D[31:24]⁽¹⁾	–	–	–	D[31:24]	D[31:24]	D[31:24]
A0/NBS0	A0	–	NLB	–	NLB⁽²⁾	BE0
A1/NWR2/NBS2/DQM2	A1	A0	A0	WE⁽³⁾	NLB⁽⁴⁾	BE2
A[22:2]⁽¹⁾	A[22:2]	A[21:1]	A[21:1]	A[20:0]	A[20:0]	A[20:0]
A[23:25]⁽¹⁾	A[23:25]	A[22:24]	A[22:24]	A[21:23]	A[21:23]	A[21:23]
NCS0	CS	CS	CS	CS	CS	CS
NCS1/DDRSDCS	CS	CS	CS	CS	CS	CS
NCS2⁽¹⁾	CS	CS	CS	CS	CS	CS
NCS3/NANDCS	CS	CS	CS	CS	CS	CS
NCS4⁽¹⁾	CS	CS	CS	CS	CS	CS
NCS5⁽¹⁾	CS	CS	CS	CS	CS	CS
NRD	OE	OE	OE	OE	OE	OE
NWR0/NWE	WE	WE⁽⁵⁾	WE	WE⁽³⁾	WE	WE
NWR1/NBS1	–	WE⁽⁵⁾	NUB	WE⁽³⁾	NUB⁽²⁾	BE1
NWR3/NBS3/DQM3	–	–	–	WE⁽³⁾	NUB⁽⁴⁾	BE3

Note:

D[31:24] and A20, A[25:23], NCS2, NCS4, NCS5 are multiplexed on PD[21:15].
NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word.
NWRx enables corresponding byte x writes (x = 0, 1, 2 or 3).
NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word.
NWR1 enables upper byte writes. NWR0 enables lower byte writes.

Table 3-4. EBI Pins and External Device Connections
Signals: EBI_	Power supply	Pins of the Interfaced Device
Signals: EBI_		DDR2/LPDDR	SDR/LPSDR	NAND Flash
Controller		MPDDRC	SDRAMC	NFC
D[7:0]	VDDIOM	D[7:0]	D[7:0]	NFD[7:0]⁽¹⁾
D[15:8]	VDDIOM	D[15:8]	D[15:8]	–
D[23:16]	VDDNF	–	D[23:16]	NFD[7:0]⁽¹⁾
D[31:24]	VDDNF	–	D[31:24]	–
A0/NBS0	VDDIOM	–	–	–
A1/NWR2/NBS2/DQM2	VDDIOM	–	DQM2	–
DQM[1:0]	VDDIOM	DQM[1:0]	DQM[1:0]	–
DQS[1:0]	VDDIOM	DQS[1:0]	–	–
A[10:2]	VDDIOM	A[8:0]	A[8:0]	–
A11	VDDIOM	A9	A9	–
SDA10	VDDIOM	A10	A10	–
A12	VDDIOM	–	–	–
A[14:13]	VDDIOM	A[12:11]	A[12:11]	–
A15	VDDIOM	A13	A13	–
A16/BA0	VDDIOM	BA0	BA0	–
A17/BA1	VDDIOM	BA1	BA1	–
A18/BA2	VDDIOM	BA2	–	–
A19	VDDIOM	–	–	–
A20	VDDNF	–	–	–
A21/NANDALE	VDDNF	–	–	ALE
A22/NANDCLE	VDDNF	–	–	CLE
A[24:23]	VDDNF	–	–	–
A25	VDDNF	–	–	–
NCS0	VDDIOM	–	–	–
NCS1/DDRSDCS	VDDIOM	DDRCS	SDCS	–
NCS2	VDDNF	–	–	–
NCS3/NANDCS	VDDNF	–	–	CE
NCS4	VDDNF	–	–	–
NCS5	VDDNF	–	–	–
NANDOE	VDDNF	–	–	OE
NANDWE	VDDNF	–	–	WE
NRD	VDDIOM	–	–	–
NWR0/NWE	VDDIOM	–	–	–
NWR1/NBS1	VDDIOM	–	–	–
NWR3/NBS3/DQM3	VDDNF	–	DQM3	–
SDCK	VDDIOM	CK	CK	–
SDCK#	VDDIOM	CK#	–	–
SDCKE	VDDIOM	CKE	CKE	–
RAS	VDDIOM	RAS	RAS	–
CAS	VDDIOM	CAS	CAS	–
SDWE	VDDIOM	WE	WE	–
Pxx	VDDNF	–	–	CE
NWAIT	VDDNF	–	–	RDY

Note:

The switch NFD0_ON_D16 is used to select the NAND Flash path on D0–D7 or D16–D23, depending on memory power supplies. This switch is located in the SFR_CCFG_EBICSA register in the Special Function Register.