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3.6.2 Embedded Characteristics
- Supported Memory Devices:
- Low-power DDR1-SDRAM (LPDDR1)
- Low-cost LPDDR1 with 2 internal banks
- DDR2-SDRAM
- Arbitration Policies: Round-Robin, On Request, Bandwidth,
Quality of Service
- 4 System Bus Interfaces;
Management of all Accesses Maximizes Memory Bandwidth and Minimizes Transaction
Latency
- Bus Transfer: Word, Half Word, Byte Access
- Supported Configurations:
- 2K, 4K, 8K, 16K row address memory parts
- DDR-SDRAM with two or four internal banks (low-power DDR1-SDRAM)
- DDR-SDRAM with four or eight internal banks (DDR2-SDRAM)
- DDR-SDRAM with 16-bit data path for system-oriented word access
- One chip select for SDRAM device (256-Mbyte address space)
- Programming Facilities
- Multibank ping-pong access (up to four or eight banks opened at the same time = reduced average latency of transactions)
- Timing parameters specified by software
- Automatic refresh operation, refresh rate is programmable
- Automatic update of DS, TCR and PASR parameters (low-power DDR-SDRAM
devices)
- Energy-Saving Capabilities
- Self-Refresh, Power-Down, Active Power-Down and Deep Power-Down modes
supported
- DDR-SDRAM Power-Up Initialization by Software
- CAS Latency of 2 or 3 Supported
- Reset Function Supported (DDR2-SDRAM)
- Clock Frequency Change in Self-Refresh Mode Supported (Low-Power
DDR-SDRAM)
- Auto-precharge Command Not Used
- OCD (Off-chip Driver) Mode, ODT (On-die Termination), are Not Supported
- Abnormal Software Access and Sequencer Integrity Error Reports
- Dynamic Scrambling with User Key (No Impact on Bandwidth)
- Bus Monitor