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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
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Product Pages
SAM9X60
Home
3
Memories
3.6
DDR-SDRAM Controller (MPDDRC)
3.6.5
Functional Description
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
External Bus Interface (EBI)
3.3
Static Memory Controller (SMC)
3.4
Programmable Multibit Error Correction Code Controller (PMECC)
3.5
Programmable Multibit ECC Error Location Controller (PMERRLOC)
3.6
DDR-SDRAM Controller (MPDDRC)
3.6.1
Description
3.6.2
Embedded Characteristics
3.6.3
Block Diagram
3.6.4
Product Dependencies, Initialization Sequence
3.6.5
Functional Description
3.6.5.1
DDR-SDRAM Controller Write Cycle
3.6.5.2
DDR-SDRAM Controller Read Cycle
3.6.5.3
Refresh (Auto-Refresh Command)
3.6.5.4
Power Management
3.6.5.5
Optimized Access Functionality
3.6.5.6
Scrambling/Unscrambling Function
3.6.5.7
Clearing Scrambling Keys on Tamper Event
3.6.5.8
Register Write Protection
3.6.5.9
Bus Monitor, Performance Monitor
3.6.5.10
Security and Safety Analysis and Reports
3.6.6
Software Interface/SDRAM Organization, Address Mapping
3.6
Register Summary
3.7
SDRAM Controller (SDRAMC)
3.8
OTP Memory Controller (OTPC)
4
System Controller
5
Image Subsystem
6
Audio Subsystem
7
Security and Cryptography Subsystem
8
Connectivity Subsystem
9
USB Subsystem
10
Electrical and Mechanical Characteristics
11
Revision History
Microchip Information
3.6.5 Functional Description
