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Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Ultra-Low Power Arm® ARM926EJ-S™ Processor-Based MPU, 600 MHz, Camera, LCD, 2D Graphics, Dual 10/100 Ethernet, CAN, USB, QSPI, FLEXCOMs, AES, SHA
Product Pages
SAM9X60
  1. Home
  2. 5 Image Subsystem
  3. 5.4 Image Sensor Interface (ISI)
  4. 5.4.5 Functional Description
  5. 5.4.5.6 Register Write Protection

  • Introduction
  • Reference Document
  • 1 Overview
  • 2 CPU and Interconnect
  • 3 Memories
  • 4 System Controller
  • 5 Image Subsystem
    • 5.1 Overview
    • 5.2 LCD Controller (LCDC)
    • 5.3 2D Graphics Engine (GFX2D)
    • 5.4 Image Sensor Interface (ISI)
      • 5.4.1 Description
      • 5.4.2 Embedded Characteristics
      • 5.4.3 Block Diagram
      • 5.4.4 Product Dependencies
      • 5.4.5 Functional Description
        • 5.4.5.1 Data Timing
        • 5.4.5.2 Data Ordering
        • 5.4.5.3 Clocks
        • 5.4.5.4 Preview Path
        • 5.4.5.5 Codec Path
        • 5.4.5.6 Register Write Protection
      • 5.4.6 Register Summary
  • 6 Audio Subsystem
  • 7 Security and Cryptography Subsystem
  • 8 Connectivity Subsystem
  • 9 USB Subsystem
  • 10 Electrical and Mechanical Characteristics
  • 11 Revision History
  • Microchip Information

5.4.5.6 Register Write Protection

To prevent any single software error from corrupting ISI behavior, certain registers in the address space can be write-protected by setting the bits WPEN in ISI_WPMR.

The following registers are write-protected when ISI_WPMR.WPEN is set:
  • ISI_CFG1
  • ISI_CFG2
  • ISI_PSIZE
  • ISI_PDECF
  • ISI_Y2R_SET0
  • ISI_Y2R_SET1
  • ISI_R2Y_SET0
  • ISI_R2Y_SET1
  • ISI_R2Y_SET2

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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