3.4.1 Fast PWM Mode in ATmega328P Automotive

A clarification for the description of the COMnx1:0 in the Timer/Counter1 PWM Mode has been made.

The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 register is not double-buffered, meaning that if ICR1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICR1 value written is lower than the current value of TCNT1. Then the result will be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCR1A register, however, is double-buffered. This feature allows the OCR1A I/O location to be written anytime. When the OCR1A I/O location is written, the written value adds to the OCR1A buffer register. The OCR1A compare register will then be updated with the value in the buffer register at the next timer clock cycle TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared, and the TOV1 flag is set.

Defining TOP using the ICR1 register works well when using fixed TOP values. By using ICR1, the OCR1A register is free to be used to generate a PWM output on OC1A. However, if the base PWM frequency is changed actively (by changing the TOP value), using the OCR1A as TOP is a better choice due to its double buffer feature.

In fast PWM mode, the compare units allow the generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM. If setting the COM1x1:0 to three (see Table “Compare Output Mode, Fast PWM”), an inverted PWM output is generated. The actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x register at the compare match between OCR1x and TCNT1. Clearing (or setting) the OC1x register at the timer clock cycle, the counter is cleared (changes from TOP to BOTTOM).