27.3.4.2.1 Clock Generation

The BAUD must be set to a value that results in a TWI bus clock frequency (fSCL) equal or less than 100 kHz/400 kHz/1 MHz, dependent on the mode used by the application (Standard mode Sm/Fast mode Fm/Fast mode plus Fm+).

The low (TLOW) and high (THIGH) times are determined by the Baud Rate register (BAUD), while the rise (TRISE) and fall (TFALL) times are determined by the bus topology. Because of the wired-AND logic of the bus, TFALL will be considered as part of TLOW. Likewise, TRISE will be in a state between TLOW and THIGH until a high state has been detected.

Figure 27-14. SCL Timing
  • TLOW – Low period of SCL clock
  • TSU;STO – Set-up time for Stop condition
  • TBUF – Bus free time between Stop and Start conditions
  • THD;STA – Hold time (repeated) Start condition
  • TSU;STA – Set-up time for repeated Start condition
  • THIGH is timed using the SCL high time count from TWI.MBAUD
  • TRISE is determined by the bus impedance; for internal pull-ups. Refer to Electrical Characteristics.
  • TFALL is determined by the open-drain current limit and bus impedance; can typically be regarded as zero. Refer to Electrical Characteristics for details.

The SCL frequency is given by:

f SCL = 1 T LOW + T HIGH + T RISE

The TWI.MBAUD value is used to time both SCL high and SCL low which gives the following formula of SCL frequency:

f SCL = f CLK_PER 10 ⁢ +   2 B A U D + f CLK_PER ⋅ T RISE

If the TWI is in Fm+ mode, only TWI.MBAUD value of three or higher is supported. This means that for Fm+ mode to achieve baud rate of 1 MHz, the peripheral clock (CLK_PER) has to run at 16 MHz or faster.