22.5.5 Interrupt Flags

Name: INTFLAGS
Offset: 0x06
Reset: 0x00
Property: -

Bit 76543210 
        CAPT 
Access R/W 
Reset 0 

Bit 0 – CAPT Interrupt Flag

This bit is set when an interrupt occurs. The interrupt conditions are dependent on the Counter Mode (CNTMODE) in TCBn.CTRLB.

This bit is cleared by writing a '1' to it or when the Capture register is read in Capture mode.

Counter ModeInterrupt Flag Behavior
Periodic Interrupt modeSet when the counter reaches TOP
Timeout Check modeSet when the counter reaches TOP
Input Capture on Event modeSet when an event occurs and the Capture register is loaded, cleared when Capture is read
Input Capture Frequency Measurement modeSet on an edge when the Capture register is loaded and count initialized, cleared when Capture is read
Input Capture Pulse-Width Measurement modeSet on an edge when the Capture register is loaded, the previous edge initialized the count, cleared when Capture is read
Input Capture Frequency and Pulse-Width Measurement modeSet on second (positive or negative) edge when the counter is stopped, cleared when Capture is read
Single-Shot modeSet when counter reaches TOP
8-Bit PWM modeSet when the counter reaches CCMPL