11.4.2 Natural Order (Hardware) Priority
When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.
| Vector Number | Interrupt source | Vector Number (cont.) | Interrupt source (cont.) |
|---|---|---|---|
| 0x0 | Software Interrupt | 0x40 | U2RX |
| 0x1 | HLVD (High/Low-Voltage Detect) | 0x41 | U2TX |
| 0x2 | OSF (Oscillator Fail) | 0x42 | U2E |
| 0x3 | CSW (Clock Switching) | 0x43 | U2 |
| 0x4 | TU16A (Universal Timer 16A) | 0x44 | TMR5 |
| 0x5 | CLC1 (Configurable Logic Cell) | 0x45 | TMR5G |
| 0x6 | CAN (CAN general) | 0x46 | CCP2 |
| 0x7 | IOC (Interrupt-On-Change) | 0x47 | SCAN |
| 0x8 | INT0 | 0x48 | U3RX |
| 0x9 | ZCD (Zero-Cross Detection) | 0x49 | U3TX |
| 0xA | AD (ADC Conversion Complete) | 0x4A | U3E |
| 0xB | ACT (Active Clock Tuning) | 0x4B | U3 |
| 0xC | CM1 (Comparator) | 0x4C | — |
| 0xD | SMT1 (Signal Measurement Timer) | 0x4D | CLC4 |
| 0xE | SMT1PRA | 0x4E | PWM4RINT |
| 0xF | SMT1PWA | 0x4F | PWM4GINT |
| 0x10 | ADT/ADCH1 (ADC Context 1) | 0x50 | INT2 |
| 0x11 | ADCH2 (ADC Context 2) | 0x51 | CLC5 |
| 0x12 | ADCH3 (ADC Context 3) | 0x52 | CWG2 (Complementary Waveform Generator) |
| 0x13 | ADCH4 (ADC Context 4) | 0x53 | NCO2 |
| 0x14 | DMA1SCNT (Direct Memory Access) | 0x54 | DMA3SCNT |
| 0x15 | DMA1DCNT | 0x55 | DMA3DCNT |
| 0x16 | DMA1OR | 0x56 | DMA3OR |
| 0x17 | DMA1A | 0x57 | DMA3A |
| 0x18 | SPI1RX (Serial Peripheral Interface) | 0x58 | CCP3 |
| 0x19 | SPI1TX | 0x59 | CLC6 |
| 0x1A | SPI1 | 0x5A | CWG3 |
| 0x1B | TMR2 | 0x5B | TMR4 |
| 0x1C | TMR1 | 0x5C | DMA4SCNT |
| 0x1D | TMR1G | 0x5D | DMA4DCNT |
| 0x1E | CCP1 (Capture/Compare/PWM) | 0x5E | DMA4OR |
| 0x1F | TMR0 | 0x5F | DMA4A |
| 0x20 | U1RX | 0x60 | U4RX |
| 0x21 | U1TX | 0x61 | U4TX |
| 0x22 | U1E | 0x62 | U4E |
| 0x23 | U1 | 0x63 | U4 |
| 0x24 | CANRX (CAN receive) | 0x64 | DMA5SCNT |
| 0x25 | CANTX (CAN transmit) | 0x65 | DMA5DCNT |
| 0x26 | PWM1RINT | 0x66 | DMA5OR |
| 0x27 | PWM1GINT | 0x67 | DMA5A |
| 0x28 | SPI2RX | 0x68 | U5RX |
| 0x29 | SPI2TX | 0x69 | U5TX |
| 0x2A | SPI2 | 0x6A | U5E |
| 0x2B | TU16B (Universal Timer 16B) | 0x6B | U5 |
| 0x2C | TMR3 | 0x6C | DMA6SCNT |
| 0x2D | TMR3G | 0x6D | DMA6DCNT |
| 0x2E | PWM2RINT | 0x6E | DMA6OR |
| 0x2F | PWM2GINT | 0x6F | DMA6A |
| 0x30 | INT1 | 0x70 | — |
| 0x31 | CLC2 | 0x71 | CLC7 |
| 0x32 | CWG1 (Complementary Waveform Generator) | 0x72 | CM2 |
| 0x33 | NCO1 (Numerically Controlled Oscillator) | 0x73 | NCO3 |
| 0x34 | DMA2SCNT | 0x74 | DMA7SCNT |
| 0x35 | DMA2DCNT | 0x75 | DMA7DCNT |
| 0x36 | DMA2OR | 0x76 | DMA7OR |
| 0x37 | DMA2A | 0x77 | DMA7A |
| 0x38 | I2C1RX | 0x78 | NVM |
| 0x39 | I2C1TX | 0x79 | CLC8 |
| 0x3A | I2C1 | 0x7A | CRC (Cyclic Redundancy Check) |
| 0x3B | I2C1E | 0x7B | TMR6 |
| 0x3C | — | 0x7C | DMA8SCNT |
| 0x3D | CLC3 | 0x7D | DMA8DCNT |
| 0x3E | PWM3RINT | 0x7E | DMA8OR |
| 0x3F | PWM3GINT | 0x7F | DMA8A |
| 0x80 - 0x8F | — |
The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.
For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).
The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.