23.5.2 CLKRCLK

Clock Reference Clock Selection Register

Name:	CLKRCLK
Address:	0x03A


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] CLKR Clock Selection

Table 23-2. Clock Reference Module Clock Sources
CLK	Clock Source
`11111-10010`	Reserved
`10001`	CLC8_OUT
`10000`	CLC7_OUT
`01111`	CLC6_OUT
`01110`	CLC5_OUT
`01101`	CLC4_OUT
`01100`	CLC3_OUT
`01011`	CLC2_OUT
`01010`	CLC1_OUT
`01001`	NCO3_OUT
`01000`	NCO2_OUT
`00111`	NCO1_OUT
`00110`	EXTOSC
`00101`	SOSC
`00100`	MFINTOSC (32 kHz)
`00011`	MFINTOSC (500 kHz)
`00010`	LFINTOSC
`00001`	HFINTOSC
`00000`	F_OSC

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