14.2.4 BOR Is Always Off

When the BOREN Configuration bits are programmed to ‘b00, the BOR is off at all times. The device start-up is not delayed by the BOR Ready condition or the V_DD level.

Table 14-1. Reset Condition for Special Registers
Condition	Program Counter	STATUS Register^(1,2)	PCON0 Register	PCON1 Register
Power-on Reset	0	`-110 0000`	`0011 110x`	`---- -111`
Brown-out Reset	0	`-110 0000`	`0011 11u0`	`---- -u1u`
MCLR Reset during normal operation	0	`-uuu uuuu`	`uuuu 0uuu`	`---- -uuu`
MCLR Reset during Sleep	0	`-10u uuuu`	`uuuu 0uuu`	`---- -uuu`
WDT Time-out Reset	0	`-0uu uuuu`	`uuu0 uuuu`	`---- -uuu`
WDT Wake-up from Sleep	PC + 2	`-00u uuuu`	`uuuu uuuu`	`---- -uuu`
WWDT Window Violation Reset	0	`-uuu uuuu`	`uu0u uuuu`	`---- -uuu`
Interrupt Wake-up from Sleep	PC + 2⁽³⁾	`-10u uuuu`	`uuuu uuuu`	`---- -uuu`
RESET Instruction Executed	0	`-uuu uuuu`	`uuuu u0uu`	`---- -uuu`
Stack Overflow Reset (STVREN = `1`)	0	`-uuu uuuu`	`1uuu uuuu`	`---- -uuu`
Stack Underflow Reset (STVREN = `1`)	0	`-uuu uuuu`	`u1uu uuuu`	`---- -uuu`
Data Protection (Fuse Fault)	0	`-uuu uuuu`	`uuuu uuuu`	`---- -uu0`
VREG or ULP Ready Fault	0	`-110 0000`	`0011 110u`	`---- -0u1`
Memory Violation Reset	0	`-uuu uuuu`	`uuuu uuuu`	`---- -u0u`
Legend: `u` = unchanged, `x` = unknown, - = unimplemented bit, reads as ‘`0`’. Note: If a Status bit is not implemented, that bit will be read as ‘`0`’. Status bits Z, C, DC are reset by POR/BOR. When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or low priority) after execution of PC + 2.

Table 14-2. BOR Operating Modes
BOREN	SBOREN	Device Mode	BOR Mode	Instruction Execution upon:
BOREN	SBOREN	Device Mode	BOR Mode	Release of POR	Wake-up from Sleep
`11`⁽¹⁾	X	X	Active	Wait for release of BOR (BORRDY = `1`)	Begins immediately
`10`	X	Awake	Active	Wait for release of BOR (BORRDY = `1`)	N/A
`10`	X	Sleep	Hibernate	N/A	Wait for release of BOR (BORRDY = `1`)
`01`	`1`	X	Active	Wait for release of BOR (BORRDY = `1`)	Begins immediately
`01`	`0`	X	Hibernate	Wait for release of BOR (BORRDY = `1`)	Begins immediately
`00`	X	X	Disabled	Begins immediately

Note:

In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no BOR ready delay in start-up. The BOR ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN bits.

Figure 14-2. Brown-Out Situations

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