3.2.5 DDR Controller

The SAMA7G5 MPU embeds a Universal DDR Memory Controller (UDDRC) to drive the DDR2, DDR3, LPDDR2 and LPDDR3 memories.

The following figure shows the UDDRC controller schematic and controller layout recommendations.

The UDDRC I/Os embed an automatic impedance matching control to avoid overshoots and to reach the best performance levels depending on the bus load and external memories. A serial termination connection scheme, where the driver has an output impedance matched to the characteristic impedance of the line, is used to improve signal quality and reduce EMI. This is done using the ZQ calibration procedure to calibrate the SAMA7G5 DDR I/O drive strength. The pin name where the ZQ resistor must be connected is DDR_ZQ, and as indicated in the SAMA7G5 Series data sheet for the DDR3L case, the resistor value is 240 Ohms.

The DDR_VREF pin serves as a voltage reference input for the DDR I/Os when DDR or LPDDR external SDRAM memories are used.