3.2.2 Configuration and Control

This figure shows the main block for processor configuration and control.

Figure 3-10. Processor Main Configuration and Control

Table 3-4. Processor Main Configuration and Control Pins
Pin Name	Type	Used for
XIN	Input	Main clock oscillator input
XOUT	Output	Main clock oscillator output
XIN32	Input	Slow clock oscillator input
XOUT32	Output	Slow clock oscillator output
NRST	Input	Processor main reset input
NRST_OUT	Output	Processor reset output
TST	Input	Reserved for processor manufacturing tests
JTAGSEL	Input	When pulled high enables the JTAG boundary scan
SHDN	Output	Signal used to enable and disable an external power supply circuit
LPM	Output	Signal used to enable and disable the PMIC Low-Power mode
WKUP0	Input	Event detection input pin used to wake up the processor from Shutdown state
QSPI0_CAL	Input	QSPI calibration
SDMMC0_CAL	Input	SDMMC0 calibration
SDMMC1_CAL	Input	SDMMC1 calibration
SDMMC2_CAL	Input	SDMMC2 calibration
AUDIOCLK	Output	Audio clock output
ADVREFP	Input	Voltage reference for the embedded analog comparator
HHSx_Dx	I/O	Three USB ports embedded inside the MPU
HHSx_RTUNE	Input	USB external tuning
MIPI_CLK_[P-N]	Input	MIPI differential input clock lanes
MIPI_DP[0-1]	Input	MIPI differential input data lanes
MIPI_REXT	Input	MIPI calibration