3.1 ATSAMR34J18B SiP Description

The ATSAMR34J18B device is an ultra-low power microcontroller equipped with a UHF transceiver. It uses the 32-bit ARM Cortex-M0+ processor at the maximum 48 MHz (2.46 CoreMark/MHz) and offers 256 KB of Flash, 32 KB of SRAM and 8 KB of low power SRAM. Sophisticated power management technologies, such as power domain gating, SleepWalking, ultra-low power peripherals and more, allow for very low line-power consumptions.

The UHF transceiver supports LoRa and FSK modulation schemes. The LoRa technology is optimized for long-range communication with minimal line-power demand. The transceiver can work from 863 MHz to 928 MHz. The maximum transmit power is +18.59 dBm without an external amplification. Operational frequency bands and power limits are defined by local regulations and the LoRa Alliance. LoRa network stack regional options ensure compliance.

All devices have accurate low power external and internal oscillators. Different clock domains can be independently configured to run at different frequencies, enabling power-saving by running each peripheral at its optimal clock frequency, thus maintaining a high CPU frequency while reducing power consumption.

The ATSAMR34J18B device supports the following software-selectable sleep modes:
  • Standby – All the clocks and functions are stopped except those selected to continue running, and all the RAMs and logic contents are retained.
  • Backup – Allows achieving the lowest power consumption. In this mode, the device is entirely powered off except for the backup domain. The internal regulator is turned off and the power manager allows retaining the state of the I/O lines, preventing I/O lines from toggling during wake-up. The external wake-up function is active and the debounce counter is running if at least one external wake-up pin is enabled.
The ATSAMR34J18B device supports SleepWalking, which allows some peripherals to wake-up from sleep based on predefined conditions. Thus, allowing some internal operations like DMA transfer and/or the CPU to wake up only when needed; for example, when a threshold is crossed or a result is ready. The event system supports synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in Standby mode.

The ATSAMR34J18B device has two software selectable performance levels (PL0 and PL2), allowing the user to scale down to the lowest core voltage level that supports the operating frequency.

The device utilizes a power domain gating technique with retention to turn off some logic areas to minimize leakage current consumption while retaining their logic states. This technique is fully handled by hardware.

The Flash program memory can be reprogrammed through the Serial Wire Debug (SWD) interface. The same interface can also be used for non-intrusive, on-chip debugging of application code.

The ATSAMR34J18B device is supported with a full suite of programs and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits.