27.5.3 Master Control A

Name: MCTRLA
Offset: 0x03
Reset: 0x00
Property: -

Bit 76543210 
 RIENWIEN QCENTIMEOUT[1:0]SMENENABLE 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – RIEN Read Interrupt Enable

Writing this bit to '1' enables interrupt on the Master Read Interrupt Flag (RIF) in the Master Status register (TWIn.MSTATUS). A TWI Master read interrupt would be generated only if this bit, the RIF, and the Global Interrupt Flag (I) in CPU.SREG are all '1'.

Bit 6 – WIEN Write Interrupt Enable

Writing this bit to '1' enables interrupt on the Master Write Interrupt Flag (WIF) in the Master Status register (TWIn.MSTATUS). A TWI Master write interrupt will be generated only if this bit, the WIF, and the Global Interrupt Flag (I) in CPU.SREG are all '1'.

Bit 4 – QCEN Quick Command Enable

Writing this bit to '1' enables Quick Command. When Quick Command is enabled, the corresponding interrupt flag is set immediately after the slave acknowledges the address. At this point, the software can either issue a Stop command or a repeated Start by writing either the Command bits (CMD) in the Master Control B register (TWIn.MCTRLB) or the Master Address register (TWIn.MADDR).

Bits 3:2 – TIMEOUT[1:0] Inactive Bus Timeout

Setting the inactive bus timeout (TIMEOUT) bits to a non-zero value will enable the inactive bus time-out supervisor. If the bus is inactive for longer than the TIMEOUT setting, the bus state logic will enter the Idle state.

ValueNameDescription
0x0 DISABLED Bus timeout disabled. I2C.
0x1 50US 50 µs - SMBus (assume baud is set to 100 kHz)
0x2 100US 100 µs (assume baud is set to 100 kHz)
0x3 200US 200 µs (assume baud is set to 100 kHz)

Bit 1 – SMEN Smart Mode Enable

Writing this bit to '1' enables the Master Smart mode. When Smart mode is enabled, the acknowledge action is sent immediately after reading the Master Data (TWIn.MDATA) register.

Bit 0 – ENABLE Enable TWI Master

Writing this bit to '1' enables the TWI as master.