7.10.4.5 System Configuration 0
| Name: | SYSCFG0 |
| Offset: | 0x05 |
| Reset: | - |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CRCSRC[1:0] | RESERVED | RSTPINCFG[1:0] | RESERVED | EESAVE | |||||
| Access | R | R | R | R | R | R | R | ||
| Reset | 1 | 1 | 1 | 0 | 1 | 1 | 0 | ||
Bits 7:6 – CRCSRC[1:0] CRC Source
| Value | Name | Description |
|---|---|---|
| 0x0 | FLASH | CRC of full Flash (boot, application code and application data) |
| 0x1 | BOOT | CRC of the boot section |
| 0x2 | BOOTAPP | CRC of application code and boot sections |
| 0x3 | NOCRC | No CRC |
Bit 5 – RESERVED
Bits 3:2 – RSTPINCFG[1:0] Reset Pin Configuration
Note: When
configuring the Reset Pin as GPIO, there is a potential conflict between the
GPIO actively driving the output, and a 12V UPDI enable sequence initiation. To
avoid this, the GPIO output driver is disabled for 768 OSC32K cycles after a
System Reset. Enable any interrupts for this pin only after this
period.
| Value | Description |
|---|---|
| 0x0 | GPIO |
| 0x1 | UPDI |
| 0x2 | RESET |
| Other | Reserved |
Bit 1 – RESERVED
Bit 0 – EESAVE EEPROM Save during chip erase
Note: If the device is locked, the
EEPROM is always erased by a chip erase, regardless of this bit.
| Value | Description |
|---|---|
| 0 | EEPROM erased during chip erase |
| 1 | EEPROM not erased under chip erase |