25.3.2.1 Clock Generation

The clock used for baud rate generation and for shifting and sampling data bits is generated internally by the fractional Baud Rate Generator or externally from the transfer clock (XCK) pin. Five modes of clock generation are supported; Normal and Double-Speed Asynchronous mode, Master and Slave Synchronous mode, and Master SPI mode.

Figure 25-2. Clock Generation Logic Block Diagram