24.11.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x00
Property: -

Bit 76543210 
 RUNSTDBYPRESCALER[3:0]  RTCEN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – RUNSTDBY Run in Standby

ValueDescription
0RTC disabled in Standby Sleep mode
1RTC enabled in Standby Sleep mode

Bits 6:3 – PRESCALER[3:0] Prescaler

These bits define the prescaling of the CLK_RTC clock signal. Due to synchronization between the RTC clock and system clock domains, there is a latency of two RTC clock cycles from updating the register until this has an effect. Application software needs to check that the CTRLABUSY flag in RTC.STATUS is cleared before writing to this register.

ValueNameDescription
0x0DIV1RTC clock/1 (no prescaling)
0x1DIV2RTC clock/2
0x2DIV4RTC clock/4
0x3DIV8RTC clock/8
0x4DIV16RTC clock/16
0x5DIV32RTC clock/32
0x6DIV64RTC clock/64
0x7DIV128RTC clock/128
0x8DIV256RTC clock/256
0x9DIV512RTC clock/512
0xADIV1024RTC clock/1024
0xBDIV2048RTC clock/2048
0xCDIV4096RTC clock/4096
0xDDIV8192RTC clock/8192
0xEDIV16384RTC clock/16384
0xFDIV32768RTC clock/32768

Bit 0 – RTCEN RTC Enable

ValueDescription
0RTC disabled
1RTC enabled