25.5.9 Control C - Master SPI Mode

This register description is valid only when the USART is in Master SPI mode (CMODE written to MSPI). For other CMODE values, see Control C - Async Mode.

See 25.3.2.5 USART in Master SPI mode for a full description of the Master SPI mode operation.

Name: CTRLC
Offset: 0x07
Reset: 0x00
Property: -

Bit 76543210 
 CMODE[1:0]   UDORDUCPHA  
Access R/WR/WR/WR/W 
Reset 0000 

Bits 7:6 – CMODE[1:0] USART Communication Mode

Writing these bits select the communication mode of the USART.

Writing a value different than 0x3 to these bits alters the available bit fields in this register, see Control C - Async Mode.

ValueNameDescription
0x0ASYNCHRONOUSAsynchronous USART
0x1SYNCHRONOUSSynchronous USART
0x2IRCOMInfrared Communication
0x3MSPIMaster SPI

Bit 2 – UDORD Data Order

Writing this bit selects the frame format.

The receiver and transmitter use the same setting. Changing the setting of UDORD will corrupt all ongoing communication for both the receiver and the transmitter.

ValueDescription
0MSB of the data word is transmitted first
1LSB of the data word is transmitted first