23.5.3 Control C

Name: CTRLC
Offset: 0x02
Reset: 0x00
Property: -

Bit 76543210 
 CMPDSELCMPCSEL  FIFTY AUPDATECMPOVR 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – CMPDSEL Compare D Output Select

ValueNameDescription
0 PWMA Waveform A
1 PWMB Waveform B

Bit 6 – CMPCSEL Compare C Output Select

ValueNameDescription
0 PWMA Waveform A
1 PWMB Waveform B

Bit 3 – FIFTY Fifty Percent Waveform

If the two waveforms have identical characteristics, this bit can be written to ‘1’. This will cause any values written to register TCDn.CMPBSET/TCDn.CLR also to be written to the register TCDn.CMPASET/TCDn.CLR.

Bit 1 – AUPDATE Automatically Update

If this bit is written to ‘1’ a synchronization at the end of the TCD cycle is automatically requested after the Compare B Clear High register (TCDn.CMPBCLRH) is written.

If the fifty percent waveform is enabled by setting the FIFTY bit in this register, writing the Compare A Clear High register will also request a synchronization at the end of the TCD cycle if the AUPDATE bit is set.

Bit 0 – CMPOVR Compare Output Value Override

When this bit is written to ‘1’, default values of the Waveform Outputs A and B are overridden by the values written in the Compare x Value in active state bit fields in the Control D register (CMPnxVAL bit in TCDn.CTRLD.). See the Control D register description for more details.