38.4.1 External Clock/Oscillator Timing Requirements

Figure 38-5. Clock Timing
Note: See the table below.
Table 38-7. 
Standard Operating Conditions (unless otherwise stated)
Param No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
ECL Oscillator
OS1FECLClock Frequency500kHz
OS2TECL_DCClock Duty Cycle4060%
ECM Oscillator
OS3FECMClock Frequency8MHz
OS4TECM_DCClock Duty Cycle4060%
ECH Oscillator
OS5FECHClock Frequency64MHz
OS6TECH_DCClock Duty Cycle4060%
LP Oscillator
OS7FLPClock Frequency100kHzNote 4
XT Oscillator
OS8FXTClock Frequency4MHzNote 4
HS Oscillator
OS9FHSClock Frequency20MHzVDD > 2.5V, Note 4
Secondary Oscillator
OS10FSECClock Frequency32.432.76833.1kHzNote 4
System Oscillator
OS20FOSCSystem Clock Frequency64MHz(Note 2, Note 3)
OS21FCYInstruction FrequencyFOSC/4MHz
OS22TCYInstruction Period62.51/FCYns
Note:
  1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.
  2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Power Saving Operation Modes” section.
  3. The system clock frequency (FOSC) must meet the voltage requirements defined in the "Standard Operating Conditions" section.
  4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used.