25.8.6 Interrupt Mask Register

Name: IMR
Offset: 0x18
Reset: 0x00000000
Property: Read-Only

Bit 3130292827262524 
        URAD 
Access R 
Reset 0 
Bit 2322212019181716 
 RSU[3:0]REC[3:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 15141312111098 
 RWC[3:0]RBE[3:0] 
Access RRRRRRRR 
Reset 00000000 
Bit 76543210 
 RDM[3:0]RHC[3:0] 
Access RRRRRRRR 
Reset 00000000 

Bit 24 – URAD Undefined Register Access Detection Interrupt Mask

ValueDescription
0The interrupt is disabled.
1The interrupt is enabled.

Bits 23:20 – RSU[3:0] Region Status Updated Interrupt Mask

ValueDescription
0When RSU[i] is reading '0', the interrupt is disabled for region i.
1When RSU[i] is reading '1', the interrupt is enabled for region i.

Bits 19:16 – REC[3:0] Region End bit Condition Detected Interrupt Mask

ValueDescription
0When REC[i] is reading '0', the interrupt is disabled for region i.
1When REC[i] is reading '1', the interrupt is enabled for region i.

Bits 15:12 – RWC[3:0] Region Wrap Condition Detected Interrupt Mask

ValueDescription
0When RWC[i] is reading '0', the interrupt is disabled for region i.
1When RWC[i] is reading '1', the interrupt is enabled for region i.

Bits 11:8 – RBE[3:0] Region Bus Error Interrupt Mask

ValueDescription
0When RBE[i] is reading '0', the interrupt is disabled for region i.
1When RBE[i] is reading '1', the interrupt is enabled for region i.

Bits 7:4 – RDM[3:0] Region Digest Mismatch Interrupt Mask

ValueDescription
0When RDM[i] is reading '0', the interrupt is disabled for region i.
1When RDM[i] is reading '1', the interrupt is enabled for region i.

Bits 3:0 – RHC[3:0] Region Hash Completed Interrupt Mask

ValueDescription
0When RHC[i] is reading '0', the interrupt is disabled for region i.
1When RHC[i] is reading '1', the interrupt is enabled for region i.